In IC designs, computer simulation processes are used to check integrity of the design and predict behavior of a resulting circuit. However, traditional processes generate a netlist from an entire physical chip layout without identifying devices, circuits, and modules of interest. As such, the presence of dummy modules makes computer simulation inefficient and may require a manual review which is time consuming and potentially adds unintended human error.
A need therefore exists for methodology and an associated system enabling a prioritizing of devices, circuits, and modules of interest, particularly in a netlist corresponding to an entire physical chip layout that includes many dummy devices (e.g., devices not of interest).